1. Field of the Invention
The present invention relates to a level conversion circuit for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between said first level and a third voltage level, and including between first and second poles of a DC supply source the series connection of the main paths of a first transistor and of a second transistor, to the control electrode of which said input signal is applied.
2. Description of the Prior Art
Such a level conversion circuit is already known in the art, e.g. from the published European patent application EEP 0 388 074 A1. Therein, the first and second transistors are of opposite conductivity type and two further third and fourth transistors are coupled between the two DC supply poles in a similar way as the first and second transistors and in parallel to the series connection of the latter transistors. The first and third transistors are of PMOS conductivity type, and the second and fourth transistors are of NMOS conductivity type. The complement of the input signal is applied to the gate electrode of the third transistor. The junction point between the third and fourth transistors constitutes a true output terminal of the level conversion circuit, and the junction point between the first and the second transistor constitutes a complemented output terminal. The gate electrode of the second transistor is connected to the true output terminal, whereas the gate electrode of the fourth transistor is connected to the complemented output terminal. The voltage provided at the first DC supply pole is 0 volts and the voltage provided at the second DC supply pole is 5 volts.
Such a level conversion circuit is for instance used to convert a digital input signal varying between 0 volts and 3.3 volts to a digital output signal varying between 0 volts and 5 volts, the digital input signal being provided by circuitry operating with a 3.3 volt supply voltage as is necessary when the conductor line widths are so small and the gate oxide layers are so thin that the use of e.g. a 5 volts supply voltage would cause problems of metal electromigration and hot electron effects, respectively. The latter digital signal is then applied to circuitry operating with a 5 volt supply voltage. To be noted that the problem of metal electromigration is due to the current through the conductor, i.e. smaller conductor line widths necessitate lower currents and thus lower supply voltages.
When the input signal is high, i.e. 3.3 volts, the first transistor is turned on and the third transistor is turned off. As a result, the voltage at the complemented output is low and the fourth transistor is turned on, thereby causing the voltage at the true output terminal to be high and the second transistor to be turned off. Across the main paths as well as across the gate drain junctions of both the second transistor and the third transistor a voltage drop of 5 volt is produced. Across the gate drain junction of the fourth transistor also a voltage drop of 5 volt is produced. For an input signal which is low similar conclusions apply.
Thus, it is clear that together with the input signal a complemented version thereof is needed in the above level conversion circuit. Furthermore, when the level conversion circuit is integrated on a chip operating with a 3.3 volt power supply necessary because of small line widths and thin gate oxide layers thereon, then problems due to metal electromigration and hot electron effects may occur since voltage drops across the transistors may rise up to 5 volts instead of the maximum allowed 3.3 volts, which is the maximum of the input voltage.